openPCIE

The openPCIE project aims to provide open-source implementations of PCIe Root Complex (RC) IP blocks for Artix-7 FPGA, marking a significant advancement in the accessibility of PCIe technology. It addresses the growing need for critical open-source IP blocks, as advocated by the European Sovereignty in open-source hardware and software roadmap. This innovative project is built around four fundamental elements:

1. openRTL - The project establishes a solid base for the design and implementation of the PCIe Root Complex IP.
2. openBFM - A unique simulation setup offers performance improvements over traditional vendor tools, facilitating faster development cycles.
3. openSW stack - A full software stack is developed alongside to ensure seamless integration and functionality.
4. openBackplane - A customized backplane for supporting the PCIe architecture allows users to build robust computing systems without the constraints of proprietary hardware.

Overview

The focus of openPCIE is to democratize FPGA-based PCIe systems by enabling users to interact directly with PCIe-based peripherals from their custom RISC-V System on Chips (SoCs). Historically, PCIe devices on motherboards have been controlled by proprietary Root Complex chips, which limited programmability and flexibility. By establishing an open-source Root Complex powered by the Artix-7 FPGA, this project changes that dynamic, thus empowering the maker community.

Immediate Goals

• Develop an open-source PCIe Root Complex tailored for the Artix-7 FPGA, interfacing with Xilinx Series7 Hard Macros and leveraging additional software and drivers.
• Construct a mini PCIE backplane that eliminates the need for soldered-down RC chips, significantly simplifying the development of open Compute systems.
• Promote the integration of existing open-source PCIe Endpoint designs, paving the way for an inclusive ecosystem.

Future Aspirations

The long-term vision of openPCIE involves the gradual replacement of proprietary components with open-source alternatives, facilitating the creation of a complete open-source PCIe stack. This endeavor is ambitious but crucial for fostering innovation in high-speed and mixed-signal designs, as advanced technology continues to evolve.

Architectural Breakdown

The project utilizes the SQRL Acorn CLE-215+ FPGA development board, which hosts the Xilinx Artix-7 XC7A200T FPGA chip. This board serves as the heart of the system, supporting various PCIe functionalities through a modular design. The entire configuration involves:

• M.2 FPGA Module - Houses the FPGA for core processing and connectivity.
• PCIe Adapter Board - Converts M.2 interface to standard PCIe for integration into test environments.

The development workflow follows a structured approach, including rigorous simulation and debugging phases to ensure functionality and reliability. Co-simulation environments employing models such as the VProc will enable developers to run comprehensive test scenarios.

The implementation leverages the capabilities of the Xilinx Vivado Design Suite to generate PCIe cores, custom RTL logic, and robust testing methodologies to ensure verification of operations across both Windows and Linux environments.

Community and Collaboration

The project has garnered support from organizations like NLnet Foundation and collaboration with envox.eu for backplane PCB development. These partnerships foster a collaborative environment aimed at enhancing the open-source hardware landscape.

With features like direct memory access through demonstration applications and extensive documentation, the openPCIE project presents a vital resource for developers seeking to explore the vast possibilities of PCIe technology in an open-source framework. An ongoing commitment to transparency and community involvement will continue to guide this initiative as it develops.