openCologne is an innovative project aimed at enhancing the CologneChip's GateMate FPGA by developing an advanced hardware platform equipped with a wide array of engaging demos and examples. This initiative focuses on fostering community engagement and promoting open-source development within the European FPGA landscape.

Overview

The CologneChip, as one of the few FPGA vendors in Europe, offers the GateMate device, which features a unique architecture that distinguishes it from mainstream alternatives. It utilizes 2-input LUT trees and multiplexers, differing from the more common microRAM-based LUT architectures. This project not only builds upon the strengths of the GateMate technology but also aims to create a supportive ecosystem for hardware developers.

Objectives

The strategy to achieve the project's goals is built on three main pillars:

1. Introduction of the ULX5M Board: This new board will replace the LatticeSemi FPGA with the GateMate architecture while maintaining compatibility with the popular Raspberry Pi Compute Module 4 (CM4). This ensures easy integration with various existing peripherals and applications, effectively expanding the usability of the first and only EU FPGA.

2. Development of Documented Examples: A comprehensive suite of well-documented examples will be created to demonstrate the effective use of GateMate resources. This includes coverage of SystemVerilog, VHDL RTL, high-level synthesis design methodologies, hardware finite state machines, and software/hardware co-design techniques.

3. Collaboration with CologneChip: Ongoing engagement with CologneChip staff will address identified issues and enhance the overall usability of the GateMate platform.

Implementation Plan

The execution is organized into three progressive levels with specific milestones:

Level I – Warm Up

• Play 1: Form a development team and familiarize with the GateMate silicon. Begin with basic examples like lighting an LED, using resources such as the provided Makefile and CCF files.
• Play 2: Adapt simpler examples from the ULX3S portfolio to enable standard PMODs and GPIO-based peripherals.
• Play 3: Design additional PMOD extensions to enhance peripheral testing capabilities.

Level II – Bread and Butter

• Play 4: Port advanced ULX3S examples, focusing on FPGA capabilities without PCB constraints.
• Play 5: Adapt the TetriSaraj hardware/software project to GateMate, integrating a RISC-V microcontroller and high-speed I/O for VGA output.
• Play 6: Design and manufacture the ULX5M board.

Level III – Candy Cane

• Play 7: Develop an advanced example for using CologneChip SerDes and high-speed PLL.
• Play 8: Conduct stress tests on the FPGA device to assess performance limits and timing metrics.
• Play 9: Port components from the BetrustedSOC project to GateMate.

Community Engagement

openCologne actively encourages contributions from interested individuals. Communication channels are open for collaboration, and developers can join the dedicated Discord channel for discussions.

For further information, including ongoing discussions surrounding challenges and enhancements, visit the project's repository at openCologne GitHub. Additional context and results can also be found on CologneChip's official site.

Conclusion

Through the development of open-source tools and examples for the GateMate architecture, this initiative aspires to elevate the user experience, foster community input, and significantly contribute to the European FPGA landscape.