Revsch is a powerful Python tool designed to transform a streamlined reverse-engineering DSL into valid KiCad schematics. Whether capturing schematics with precision or enabling quick probe-first mapping, Revsch simplifies the design process, offering a self-contained output that integrates easily with KiCad's interface.
revsch is a Python-based tool designed to streamline reverse engineering workflows through a dedicated Domain-Specific Language (DSL) for KiCad schematic capture. It offers two primary workflows:
Schematic-Style Capture
This approach allows for explicit declaration of components, pins, and named nets, providing detailed control over schematic creation.
Probe-First Mapping
This efficient method facilitates quick continuity capture through simplified traces, using the syntax X -> Y, Z, which enables rapid development of schematics by batch-generating parts and utilizing minimal pin metadata.
The tool generates a valid .kicad_sch file, which can be refined further in the KiCad environment. For standard generic components, the output favors official KiCad library symbols, while custom and lesser-known parts revert to embedded generated symbols, ensuring a self-contained schematic.
Useful Commands
The following command examples illustrate the ease of use for common tasks:
uv run revsch lint examples/basic_minimal.revsch
uv run revsch compile examples/basic_minimal.revsch -o ~/tmp/basic_minimal.kicad_sch
Additional commands such as dump-json, format, and lint are also available to enhance the user experience while working with schematics.
DSL Features
The DSL supports various statement types, including:
- Parts:
part REFDES ... - Pins:
pin REFDES.PIN ... - Nets:
net NAME = REFDES.PIN, REFDES.PIN - Aliases:
alias ALT = NET - Properties and Notes:
property TARGET KEY = VALUEandnote TARGET = VALUE - Batch Generation: Use
PREFIX key=value ...for efficient part instantiation with indexed naming.
Example Usage
A schematic-style example demonstrating the declaration of components:
part U1 kind=IC value="STM32F103C8" package=LQFP48
pin U1.24 name=VDD type=power_in
net VCC_3V3 = U1.24
Another example highlights the probe-first mapping technique for rapid tracing:
IC name=PLA pincount=16 count=6
J1.1 -> +5V
C1 -> GND
JSON Output Options
Revsch provides the ability to export parsed DSL structures in JSON format through several commands, facilitating integration with other tools:
uv run revsch dump-json examples/mapping_probe.revsch
Utilizing revsch enhances the reverse engineering of electronic schematics, making the process of converting design intents into KiCad formats efficient and effective.
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